The MediaTek MT6572 has an average performing CPU with a maximum clock speed of 1,200.00 MHz. It has 2 core(s), resulting in good multi-tasking when compared to a single core processor.
As a result of following the Harvard architecture, the CPU has a separate Level 1 instruction and data cache leading to a slight improvement in performance over a unified Level 1 cache. The instruction cache is only used for storing instructions and executes in a sequential manner. The data cache stores data used by instructions; the point of access or storage is generally specified by an instruction.
This processor is based on the Reduced Instruction Set Computing (RISC) design strategy enabling instructions to execute faster, as opposed to the Complex Instruction Set Computing (CISC) design strategy, which is generally slower at executing due to lengthy instructions.